Embodiments of the invention relate generally to integrated circuit packages and, more particularly, to embedded chip build-up. Embedded chip packages are manufactured using pre-patterned laminate re-distribution layers and placement of a die relative to the pre-patterned layers.
As integrated circuits become increasingly smaller and yield better operating performance, packaging technology for integrated circuit (IC) packaging has correspondingly evolved from leaded packaging to laminated-based ball grid array (BGA) packaging and eventually to chip scale packaging (CSP). Advancements in IC chip packaging technology are driven by ever-increasing needs for achieving better performance, greater miniaturization and higher reliability. New packaging technology has to further provide for the possibilities of batch production for the purpose of large-scale manufacturing thereby allowing economy of scale.
A standard CSP manufacturing process typically begins with placement of one or more dies onto a top surface of a silicon integrated circuit (IC) substrate. A plurality of re-distribution layers are then deposited onto the IC substrate and the die(s) and are patterned to form a thin-film metal re-routing and interconnection system. The re-distribution layers are typically formed from a benzocyclobutene (BCB) or polyimide material, for example, and applied via a spin-on or lamination application process.
Deposition of the die and the re-distribution layers in this manner, however, has inherent limitations in regards to the production process and the structure and functionality of the resulting embedded chip that is produced. For example, the layer-by-layer application of the multiple re-distribution layers onto the previously placed die(s) leads to an increased fabrication cycle time. Additionally, as the re-routing and interconnection system is formed by a layer-by-layer application of the multiple re-distribution layers onto the previously placed die(s), there is no ability to pre-test the re-routing and interconnection system. Therefore, if the re-routing and interconnection system is found to be defective based on post-application (onto the die) testing, disassembly of the chip and re-working of the die increases production costs.
Advancements in IC chip packaging requirements also pose challenges to the existing embedded chip build-up process. That is, it is desired in many current embedded chip packages to have an increased number of re-distribution layers, with eight or more re-distribution layers being common. The standard embedded chip build-up process, in which the one or more dies are initially placed on the IC substrate and the re-distribution layers are subsequently applied in a layer-by-layer fashion, can be unsuitable for creating a re-routing and interconnection system with such an increased number of re-distribution layers. Application of an increased number of re-distribution layers in a layer-by-layer fashion can lead to warpage in the rerouting and interconnection system. Re-distribution layer warpage imparts stress to the silicon wafer substrate, which can impose limitations on formation of an input/output (I/O) system on the embedded chip. That is, because of the stress imparted on the silicon wafer by the re-distribution layer warpage, larger and more robust bumps (i.e., solder balls/connections) and an underfill epoxy are needed for formation of the I/O system interconnection. This limits the bump density of the I/O system and limits the level of miniaturization of the chip that is achievable.
Accordingly there is a need for a method for embedded chip fabrication that allows for the application of multiple re-distribution layers while minimizing stress and warpage of the wafer die. There is a further need for a fabrication method that provides for a shorter manufacturing cycle time and that allows for pre-testing of the re-routing and interconnection system prior to placement of the die.